cmake_minimum_required(VERSION 3.17)

project(XDCRE_TC397)

set(BasePath  ${CMAKE_CURRENT_SOURCE_DIR})

set(CMAKE_BUILD_TYPE  Release)

add_compile_options(
    --create=object
    --iso=99
    --language=-gcc,-volatile
    --switch=auto
    --align=4
    --default-near-size=0
    -Ctc39xb
    --optimize=2
    --debug-info 
    --tradeoff=0
    --compact-max-size=200
    --source
    -g
    --c++=03
    --fp-model=1
)

add_link_options(
    -lc_fpu
    -lfp_fpu
    -lrt
    -M:XML
    -M 
    -OtxycL
    -mcrfiklSmMOduQ
    -d${BasePath}/Lcf_Tasking_Tricore_Tc.lsl 
    -I${BasePath}
)

file(GLOB CommonFiles 
${BasePath}/0_Src/0_AppSw/Config/Common/Ifx_Cfg_Ssw.c
${BasePath}/0_Src/0_AppSw/Config/Common/Ifx_Cfg_SswBmhd.c
${BasePath}/0_Src/0_AppSw/Config/Common/Ifx_InterfaceConst.c
${BasePath}/0_Src/0_AppSw/Config/Common/sync_on_halt.c
)

file(GLOB LWIPFiles 
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/port/src/Ifx_Lwip.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/port/src/netif.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/api/api_lib.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/api/api_msg.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/api/err.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/api/if_api.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/api/netbuf.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/api/netdb.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/api/netifapi.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/api/sockets.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/api/tcpip.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv4/autoip.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv4/dhcp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv4/etharp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv4/icmp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv4/igmp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv4/ip4.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv4/ip4_addr.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv4/ip4_frag.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv6/dhcp6.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv6/ethip6.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv6/icmp6.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv6/inet6.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv6/ip6.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv6/ip6_addr.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv6/ip6_frag.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv6/mld6.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ipv6/nd6.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/altcp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/altcp_alloc.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/altcp_tcp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/def.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/dns.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/inet_chksum.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/init.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/ip.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/mem.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/memp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/netif.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/pbuf.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/raw.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/stats.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/sys.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/tcp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/tcp_in.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/tcp_out.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/timeouts.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/core/udp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/polarssl/arc4.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/polarssl/des.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/polarssl/md4.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/polarssl/md5.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/polarssl/sha1.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/auth.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/ccp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/chap-md5.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/chap-new.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/chap_ms.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/demand.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/eap.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/ecp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/eui64.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/fsm.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/ipcp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/ipv6cp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/lcp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/magic.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/mppe.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/multilink.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/ppp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/pppapi.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/pppcrypt.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/pppoe.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/pppol2tp.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/pppos.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/upap.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/utils.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ppp/vj.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/bridgeif.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/bridgeif_fdb.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/ethernet.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/lowpan6.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/lowpan6_ble.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/lowpan6_common.c
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/netif/zepif.c
)

file(GLOB PHYFiles 
${BasePath}/0_Src/0_AppSw/Ethernet/Phy_Dp83825i/IfxGeth_Phy_Dp83825i.c
${BasePath}/0_Src/0_AppSw/Ethernet/Phy_Rtl8211f/IfxGeth_Phy_Rtl8211f.c
)

file(GLOB MainFiles 
${BasePath}/0_Src/0_AppSw/Tricore/Main/Cpu0_Main.c
${BasePath}/0_Src/0_AppSw/Tricore/Main/Cpu1_Main.c
${BasePath}/0_Src/0_AppSw/Tricore/Main/Cpu2_Main.c
${BasePath}/0_Src/0_AppSw/Tricore/Main/Cpu3_Main.c
${BasePath}/0_Src/0_AppSw/Tricore/Main/Cpu4_Main.c
${BasePath}/0_Src/0_AppSw/Tricore/Main/Cpu5_Main.c
${BasePath}/0_Src/0_AppSw/Tricore/Main/Echo.c
${BasePath}/0_Src/0_AppSw/Tricore/Main/TricoreTime.c
)

file(GLOB UARTFiles 
${BasePath}/0_Src/0_AppSw/UART/UART_Logging.c
)

file(GLOB iLLDFiles 
${BasePath}/0_Src/1_SrvSw/If/SpiIf.c
${BasePath}/0_Src/1_SrvSw/StdIf/IfxStdIf_DPipe.c
${BasePath}/0_Src/1_SrvSw/StdIf/IfxStdIf_Pos.c
${BasePath}/0_Src/1_SrvSw/StdIf/IfxStdIf_PwmHl.c
${BasePath}/0_Src/1_SrvSw/StdIf/IfxStdIf_Timer.c
${BasePath}/0_Src/1_SrvSw/SysSe/Bsp/Assert.c
${BasePath}/0_Src/1_SrvSw/SysSe/Bsp/Bsp.c
${BasePath}/0_Src/1_SrvSw/SysSe/Comm/Ifx_Console.c
${BasePath}/0_Src/1_SrvSw/SysSe/Comm/Ifx_Shell.c
${BasePath}/0_Src/1_SrvSw/SysSe/General/Ifx_GlobalResources.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_AngleTrkF32.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_Cf32.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_Crc.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_FftF32.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_FftF32_BitReverseTable.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_FftF32_TwiddleTable.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_IntegralF32.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_LowPassPt1.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_LowPassPt1F32.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_LutAtan2F32.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_LutAtan2F32_Table.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_LutLinearF32.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_LutLSincosF32.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_LutSincosF32.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_LutSincosF32_Table.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_RampF32.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_WndF32_BlackmanHarrisTable.c
${BasePath}/0_Src/1_SrvSw/SysSe/Math/Ifx_WndF32_HannTable.c
${BasePath}/0_Src/1_SrvSw/SysSe/Time/Ifx_DateTime.c
#${BasePath}/0_Src/1_SrvSw/Tricore/Compilers/CompilerDcc.c
#${BasePath}/0_Src/1_SrvSw/Tricore/Compilers/CompilerGhs.c
#${BasePath}/0_Src/1_SrvSw/Tricore/Compilers/CompilerGnuc.c
${BasePath}/0_Src/1_SrvSw/Tricore/Compilers/CompilerTasking.c
${BasePath}/0_Src/1_SrvSw/Tricore/Compilers/Ifx_Ssw_Infra.c
${BasePath}/0_Src/1_SrvSw/Tricore/Compilers/Ifx_Ssw_Tc0.c
${BasePath}/0_Src/1_SrvSw/Tricore/Compilers/Ifx_Ssw_Tc1.c
${BasePath}/0_Src/1_SrvSw/Tricore/Compilers/Ifx_Ssw_Tc2.c
${BasePath}/0_Src/1_SrvSw/Tricore/Compilers/Ifx_Ssw_Tc3.c
${BasePath}/0_Src/1_SrvSw/Tricore/Compilers/Ifx_Ssw_Tc4.c
${BasePath}/0_Src/1_SrvSw/Tricore/Compilers/Ifx_Ssw_Tc5.c
${BasePath}/0_Src/4_McHal/Tricore/Asclin/Asc/IfxAsclin_Asc.c
${BasePath}/0_Src/4_McHal/Tricore/Asclin/Lin/IfxAsclin_Lin.c
${BasePath}/0_Src/4_McHal/Tricore/Asclin/Spi/IfxAsclin_Spi.c
${BasePath}/0_Src/4_McHal/Tricore/Asclin/Std/IfxAsclin.c
${BasePath}/0_Src/4_McHal/Tricore/Can/Can/IfxCan_Can.c
${BasePath}/0_Src/4_McHal/Tricore/Can/Std/IfxCan.c
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/Icu/IfxCcu6_Icu.c
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/PwmBc/IfxCcu6_PwmBc.c
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/PwmHl/IfxCcu6_PwmHl.c
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/Std/IfxCcu6.c
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/Timer/IfxCcu6_Timer.c
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/TimerWithTrigger/IfxCcu6_TimerWithTrigger.c
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/TPwm/IfxCcu6_TPwm.c
${BasePath}/0_Src/4_McHal/Tricore/Convctrl/Std/IfxConvctrl.c
${BasePath}/0_Src/4_McHal/Tricore/Cpu/Irq/IfxCpu_Irq.c
${BasePath}/0_Src/4_McHal/Tricore/Cpu/Std/IfxCpu.c
${BasePath}/0_Src/4_McHal/Tricore/Cpu/Trap/IfxCpu_Trap.c
${BasePath}/0_Src/4_McHal/Tricore/Dma/Dma/IfxDma_Dma.c
${BasePath}/0_Src/4_McHal/Tricore/Dma/Std/IfxDma.c
${BasePath}/0_Src/4_McHal/Tricore/Dts/Dts/IfxDts_Dts.c
${BasePath}/0_Src/4_McHal/Tricore/Dts/Std/IfxDts.c
${BasePath}/0_Src/4_McHal/Tricore/Ebu/BFlashSpansion/IfxEbu_BFlashSpansion.c
${BasePath}/0_Src/4_McHal/Tricore/Ebu/BFlashSt/IfxEbu_BFlashSt.c
${BasePath}/0_Src/4_McHal/Tricore/Ebu/Dram/IfxEbu_Dram.c
${BasePath}/0_Src/4_McHal/Tricore/Ebu/Sram/IfxEbu_Sram.c
${BasePath}/0_Src/4_McHal/Tricore/Ebu/Std/IfxEbu.c
${BasePath}/0_Src/4_McHal/Tricore/Edsadc/Edsadc/IfxEdsadc_Edsadc.c
${BasePath}/0_Src/4_McHal/Tricore/Edsadc/Std/IfxEdsadc.c
${BasePath}/0_Src/4_McHal/Tricore/Emem/Std/IfxEmem.c
${BasePath}/0_Src/4_McHal/Tricore/Eray/Eray/IfxEray_Eray.c
${BasePath}/0_Src/4_McHal/Tricore/Eray/Std/IfxEray.c
${BasePath}/0_Src/4_McHal/Tricore/Evadc/Adc/IfxEvadc_Adc.c
${BasePath}/0_Src/4_McHal/Tricore/Evadc/Std/IfxEvadc.c
${BasePath}/0_Src/4_McHal/Tricore/Fce/Crc/IfxFce_Crc.c
${BasePath}/0_Src/4_McHal/Tricore/Fce/Std/IfxFce.c
${BasePath}/0_Src/4_McHal/Tricore/Flash/Std/IfxFlash.c
${BasePath}/0_Src/4_McHal/Tricore/Geth/Eth/IfxGeth_Eth.c
${BasePath}/0_Src/4_McHal/Tricore/Geth/Std/IfxGeth.c
${BasePath}/0_Src/4_McHal/Tricore/Gpt12/IncrEnc/IfxGpt12_IncrEnc.c
${BasePath}/0_Src/4_McHal/Tricore/Gpt12/Std/IfxGpt12.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Atom/Dtm_PwmHl/IfxGtm_Atom_Dtm_PwmHl.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Atom/Pwm/IfxGtm_Atom_Pwm.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Atom/PwmHl/IfxGtm_Atom_PwmHl.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Atom/Timer/IfxGtm_Atom_Timer.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Std/IfxGtm.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Std/IfxGtm_Atom.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Std/IfxGtm_Cmu.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Std/IfxGtm_Dpll.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Std/IfxGtm_Dtm.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Std/IfxGtm_Psm.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Std/IfxGtm_Spe.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Std/IfxGtm_Tbu.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Std/IfxGtm_Tim.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Std/IfxGtm_Tom.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Tim/In/IfxGtm_Tim_In.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Tim/Timer/IfxGtm_Tim_Timer.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Tom/Dtm_PwmHl/IfxGtm_Tom_Dtm_PwmHl.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Tom/Pwm/IfxGtm_Tom_Pwm.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Tom/PwmHl/IfxGtm_Tom_PwmHl.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Tom/Timer/IfxGtm_Tom_Timer.c
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Trig/IfxGtm_Trig.c
${BasePath}/0_Src/4_McHal/Tricore/Hspdm/Std/IfxHspdm.c
${BasePath}/0_Src/4_McHal/Tricore/Hssl/Hssl/IfxHssl_Hssl.c
${BasePath}/0_Src/4_McHal/Tricore/Hssl/Std/IfxHssl.c
${BasePath}/0_Src/4_McHal/Tricore/I2c/I2c/IfxI2c_I2c.c
${BasePath}/0_Src/4_McHal/Tricore/I2c/Std/IfxI2c.c
${BasePath}/0_Src/4_McHal/Tricore/Iom/Driver/IfxIom_Driver.c
${BasePath}/0_Src/4_McHal/Tricore/Iom/Iom/IfxIom_Iom.c
${BasePath}/0_Src/4_McHal/Tricore/Iom/Std/IfxIom.c
${BasePath}/0_Src/4_McHal/Tricore/Msc/Msc/IfxMsc_Msc.c
${BasePath}/0_Src/4_McHal/Tricore/Msc/Std/IfxMsc.c
${BasePath}/0_Src/4_McHal/Tricore/Mtu/Std/IfxMtu.c
${BasePath}/0_Src/4_McHal/Tricore/Pms/Std/IfxPmsEvr.c
${BasePath}/0_Src/4_McHal/Tricore/Pms/Std/IfxPmsPm.c
${BasePath}/0_Src/4_McHal/Tricore/Port/Io/IfxPort_Io.c
${BasePath}/0_Src/4_McHal/Tricore/Port/Std/IfxPort.c
${BasePath}/0_Src/4_McHal/Tricore/Psi5/Psi5/IfxPsi5_Psi5.c
${BasePath}/0_Src/4_McHal/Tricore/Psi5/Std/IfxPsi5.c
${BasePath}/0_Src/4_McHal/Tricore/Psi5s/Psi5s/IfxPsi5s_Psi5s.c
${BasePath}/0_Src/4_McHal/Tricore/Psi5s/Std/IfxPsi5s.c
${BasePath}/0_Src/4_McHal/Tricore/Qspi/SpiMaster/IfxQspi_SpiMaster.c
${BasePath}/0_Src/4_McHal/Tricore/Qspi/SpiSlave/IfxQspi_SpiSlave.c
${BasePath}/0_Src/4_McHal/Tricore/Qspi/Std/IfxQspi.c
${BasePath}/0_Src/4_McHal/Tricore/Rif/Rif/IfxRif_Rif.c
${BasePath}/0_Src/4_McHal/Tricore/Rif/Std/IfxRif.c
${BasePath}/0_Src/4_McHal/Tricore/Scu/Std/IfxScuCcu.c
${BasePath}/0_Src/4_McHal/Tricore/Scu/Std/IfxScuEru.c
${BasePath}/0_Src/4_McHal/Tricore/Scu/Std/IfxScuLbist.c
${BasePath}/0_Src/4_McHal/Tricore/Scu/Std/IfxScuRcu.c
${BasePath}/0_Src/4_McHal/Tricore/Scu/Std/IfxScuWdt.c
${BasePath}/0_Src/4_McHal/Tricore/Sdmmc/Emmc/IfxSdmmc_Emmc.c
${BasePath}/0_Src/4_McHal/Tricore/Sdmmc/Sd/IfxSdmmc_Sd.c
${BasePath}/0_Src/4_McHal/Tricore/Sdmmc/Std/IfxSdmmc.c
${BasePath}/0_Src/4_McHal/Tricore/Sent/Sent/IfxSent_Sent.c
${BasePath}/0_Src/4_McHal/Tricore/Sent/Std/IfxSent.c
${BasePath}/0_Src/4_McHal/Tricore/Smu/Smu/IfxSmu_Smu.c
${BasePath}/0_Src/4_McHal/Tricore/Smu/Std/IfxSmu.c
${BasePath}/0_Src/4_McHal/Tricore/Smu/Std/IfxSmuStdby.c
${BasePath}/0_Src/4_McHal/Tricore/Spu/Std/IfxSpu.c
${BasePath}/0_Src/4_McHal/Tricore/Src/Std/IfxSrc.c
${BasePath}/0_Src/4_McHal/Tricore/Stm/Std/IfxStm.c
${BasePath}/0_Src/4_McHal/Tricore/Stm/Timer/IfxStm_Timer.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxAsclin_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxCan_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxCcu6_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxCif_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxCpu_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxDma_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxEmem_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxEray_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxEvadc_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxFlash_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxGeth_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxGtm_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxHspdm_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxHssl_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxI2c_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxMsc_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxMtu_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxMultican_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxPort_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxPsi5_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxQspi_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxRif_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxScu_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxSent_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxSmu_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxSpu_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxSrc_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Impl/IfxStm_cfg.c
${BasePath}/0_Src/4_McHal/Tricore/_Lib/DataHandling/Ifx_CircularBuffer.asm.c
${BasePath}/0_Src/4_McHal/Tricore/_Lib/DataHandling/Ifx_CircularBuffer.c
${BasePath}/0_Src/4_McHal/Tricore/_Lib/DataHandling/Ifx_Fifo.c
${BasePath}/0_Src/4_McHal/Tricore/_Lib/InternalMux/Ifx_InternalMux.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxAsclin_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxCan_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxCcu6_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxDmu_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxEdsadc_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxEray_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxEvadc_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxGeth_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxGpt12_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxGtm_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxHspdm_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxI2c_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxMsc_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxPms_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxPort_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxPsi5s_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxPsi5_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxQspi_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxRif_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxScu_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxSdmmc_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxSent_PinMap.c
${BasePath}/0_Src/4_McHal/Tricore/_PinMap/IfxSmu_PinMap.c
)

file(GLOB MicroCdrFiles 
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microcdr/src/c/types/array.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microcdr/src/c/types/basic.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microcdr/src/c/types/sequence.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microcdr/src/c/types/string.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microcdr/src/c/common.c
)

file(GLOB MicroDdsFiles 
#${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/examples/PublishHelloWorld/HelloWorld.c
#${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/examples/PublishHelloWorld/main.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/examples/SubscribeHelloWorld/subscriber.c
#${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/examples/SubscribeHelloWorld/example_main.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/examples/SubscribeHelloWorld/HelloWorld.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/log/log.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/serialization/xrce_header.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/serialization/xrce_subheader.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/serialization/xrce_types.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/stream/input_best_effort_stream.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/stream/input_reliable_stream.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/stream/output_best_effort_stream.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/stream/output_reliable_stream.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/stream/seq_num.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/stream/stream_id.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/stream/stream_storage.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/common_create_entities.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/create_entities_bin.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/create_entities_ref.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/create_entities_xml.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/object_id.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/read_access.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/session.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/session_info.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/submessage.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/write_access.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/profile/matching/matching.c
#${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/profile/multithread/multithread.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/profile/transport/ip/udp/udp_transport.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/profile/transport/ip/udp/udp_transport_posix_nopoll.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/profile/transport/ip/ip_posix.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/profile/transport/stream_framing/stream_framing_protocol.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/util/ping.c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/util/time.c
)



include_directories( PRIVATE
${BasePath}/0_Src/0_AppSw/Config/Common
${BasePath}/0_Src/0_AppSw/Ethernet/lwip
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/port
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/port/include
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/port/include/arch
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/compat
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/compat/posix
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/compat/posix/arpa
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/compat/posix/net
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/compat/posix/sys
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/compat/stdc
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/lwip
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/lwip/apps
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/lwip/priv
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/lwip/prot
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/netif/ppp/polarssl
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/netif/ppp
${BasePath}/0_Src/0_AppSw/Ethernet/lwip/src/include/netif
${BasePath}/0_Src/0_AppSw/Ethernet/Phy_Dp83825i
${BasePath}/0_Src/0_AppSw/Ethernet/Phy_Rtl8211f
${BasePath}/0_Src/0_AppSw/Tricore/Main
${BasePath}/0_Src/0_AppSw/UART
${BasePath}/0_Src/1_SrvSw/If
${BasePath}/0_Src/1_SrvSw/If/Ccu6If
${BasePath}/0_Src/1_SrvSw/StdIf
${BasePath}/0_Src/1_SrvSw/SysSe
${BasePath}/0_Src/1_SrvSw/SysSe/Bsp
${BasePath}/0_Src/1_SrvSw/SysSe/Comm
${BasePath}/0_Src/1_SrvSw/SysSe/General
${BasePath}/0_Src/1_SrvSw/SysSe/Math
${BasePath}/0_Src/1_SrvSw/SysSe/Time
${BasePath}/0_Src/1_SrvSw
${BasePath}/0_Src/1_SrvSw/Tricore
${BasePath}/0_Src/1_SrvSw/Tricore/Compilers
${BasePath}/0_Src/1_SrvSw/_Utilities
${BasePath}/0_Src/4_McHal/Tricore
${BasePath}/0_Src/4_McHal/Tricore/Asclin/Asc
${BasePath}/0_Src/4_McHal/Tricore/Asclin/Lin
${BasePath}/0_Src/4_McHal/Tricore/Asclin/Spi
${BasePath}/0_Src/4_McHal/Tricore/Asclin/Std
${BasePath}/0_Src/4_McHal/Tricore/Can/Can
${BasePath}/0_Src/4_McHal/Tricore/Can/Std
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/Icu
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/PwmBc
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/PwmHl
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/Std
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/Timer
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/TimerWithTrigger
${BasePath}/0_Src/4_McHal/Tricore/Ccu6/TPwm
${BasePath}/0_Src/4_McHal/Tricore/Convctrl/Std
${BasePath}/0_Src/4_McHal/Tricore/Cpu/CStart
${BasePath}/0_Src/4_McHal/Tricore/Cpu/Irq
${BasePath}/0_Src/4_McHal/Tricore/Cpu/Std
${BasePath}/0_Src/4_McHal/Tricore/Cpu/Trap
${BasePath}/0_Src/4_McHal/Tricore/Dma/Dma
${BasePath}/0_Src/4_McHal/Tricore/Dma/Std
${BasePath}/0_Src/4_McHal/Tricore/Dts/Dts
${BasePath}/0_Src/4_McHal/Tricore/Dts/Std
${BasePath}/0_Src/4_McHal/Tricore/Ebu/BFlashSpansion
${BasePath}/0_Src/4_McHal/Tricore/Ebu/BFlashSt
${BasePath}/0_Src/4_McHal/Tricore/Ebu/Dram
${BasePath}/0_Src/4_McHal/Tricore/Ebu/Sram
${BasePath}/0_Src/4_McHal/Tricore/Ebu/Std
${BasePath}/0_Src/4_McHal/Tricore/Edsadc/Edsadc
${BasePath}/0_Src/4_McHal/Tricore/Edsadc/Std
${BasePath}/0_Src/4_McHal/Tricore/Emem/Std
${BasePath}/0_Src/4_McHal/Tricore/Eray/Eray
${BasePath}/0_Src/4_McHal/Tricore/Eray/Std
${BasePath}/0_Src/4_McHal/Tricore/Evadc/Adc
${BasePath}/0_Src/4_McHal/Tricore/Evadc/Std
${BasePath}/0_Src/4_McHal/Tricore/Fce/Crc
${BasePath}/0_Src/4_McHal/Tricore/Fce/Std
${BasePath}/0_Src/4_McHal/Tricore/Flash/Std
${BasePath}/0_Src/4_McHal/Tricore/Geth/Eth
${BasePath}/0_Src/4_McHal/Tricore/Geth/Std
${BasePath}/0_Src/4_McHal/Tricore/Gpt12/IncrEnc
${BasePath}/0_Src/4_McHal/Tricore/Gpt12/Std
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Atom/Dtm_PwmHl
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Atom/Pwm
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Atom/PwmHl
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Atom/Timer
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Std
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Tim/In
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Tim/Timer
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Tom/Dtm_PwmHl
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Tom/Pwm
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Tom/PwmHl
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Tom/Timer
${BasePath}/0_Src/4_McHal/Tricore/Gtm/Trig
${BasePath}/0_Src/4_McHal/Tricore/Hspdm/Std
${BasePath}/0_Src/4_McHal/Tricore/Hssl/Hssl
${BasePath}/0_Src/4_McHal/Tricore/Hssl/Std
${BasePath}/0_Src/4_McHal/Tricore/I2c/I2c
${BasePath}/0_Src/4_McHal/Tricore/I2c/Std
${BasePath}/0_Src/4_McHal/Tricore/Iom/Driver
${BasePath}/0_Src/4_McHal/Tricore/Iom/Iom
${BasePath}/0_Src/4_McHal/Tricore/Iom/Std
${BasePath}/0_Src/4_McHal/Tricore/Msc/Msc
${BasePath}/0_Src/4_McHal/Tricore/Msc/Std
${BasePath}/0_Src/4_McHal/Tricore/Mtu/Std
${BasePath}/0_Src/4_McHal/Tricore/Pms/Std
${BasePath}/0_Src/4_McHal/Tricore/Port/Io
${BasePath}/0_Src/4_McHal/Tricore/Port/Std
${BasePath}/0_Src/4_McHal/Tricore/Psi5/Psi5
${BasePath}/0_Src/4_McHal/Tricore/Psi5/Std
${BasePath}/0_Src/4_McHal/Tricore/Psi5s/Psi5s
${BasePath}/0_Src/4_McHal/Tricore/Psi5s/Std
${BasePath}/0_Src/4_McHal/Tricore/Qspi/SpiMaster
${BasePath}/0_Src/4_McHal/Tricore/Qspi/SpiSlave
${BasePath}/0_Src/4_McHal/Tricore/Qspi/Std
${BasePath}/0_Src/4_McHal/Tricore/Rif/Rif
${BasePath}/0_Src/4_McHal/Tricore/Rif/Std
${BasePath}/0_Src/4_McHal/Tricore/Scu/Std
${BasePath}/0_Src/4_McHal/Tricore/Sdmmc/Emmc
${BasePath}/0_Src/4_McHal/Tricore/Sdmmc/Sd
${BasePath}/0_Src/4_McHal/Tricore/Sdmmc/Std
${BasePath}/0_Src/4_McHal/Tricore/Sent/Sent
${BasePath}/0_Src/4_McHal/Tricore/Sent/Std
${BasePath}/0_Src/4_McHal/Tricore/Smu/Smu
${BasePath}/0_Src/4_McHal/Tricore/Smu/Std
${BasePath}/0_Src/4_McHal/Tricore/Spu/Std
${BasePath}/0_Src/4_McHal/Tricore/Src/Std
${BasePath}/0_Src/4_McHal/Tricore/Stm/Std
${BasePath}/0_Src/4_McHal/Tricore/Stm/Timer
${BasePath}/0_Src/4_McHal/Tricore/_Impl
${BasePath}/0_Src/4_McHal/Tricore/_Lib/DataHandling
${BasePath}/0_Src/4_McHal/Tricore/_Lib/InternalMux
${BasePath}/0_Src/4_McHal/Tricore/_PinMap
${BasePath}/0_Src/4_McHal/Tricore/_Reg
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microcdr
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microcdr/include
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microcdr/src/c
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/examples/SubscribeHelloWorld
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/include
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/include/uxr
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/include/uxr/client
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/include/uxr/client/util
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/include/uxr/client/core/communication
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/include/uxr/client/core/session/stream
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/include/uxr/client/core/session
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/include/uxr/client/core/type
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/include/uxr/client/profile/multithread
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/include/uxr/client/profile/transport/ip/udp
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/include/uxr/client/profile/transport/ip
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/include/uxr/client/profile/transport/stream_framing
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/log
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/serialization
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session/stream
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/core/session
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/profile/matching
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/profile/transport/ip/udp
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/profile/transport/stream_framing
${BasePath}/0_Src/Micro-XRCE-DDS-Client/microdds/src/c/util
)

add_executable(${CMAKE_PROJECT_NAME}  ${MicroCdrFiles} ${MicroDdsFiles} ${CommonFiles}  ${LWIPFiles}
${PHYFiles} ${MainFiles} ${UARTFiles} ${iLLDFiles})